43 lines
928 B
VHDL
43 lines
928 B
VHDL
-- Code your design here
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity fulladder_struct is
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port (afa_s_i : in std_logic;
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bfa_s_i : in std_logic;
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cinfa_s_i : in std_logic;
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sumfa_s_o : out std_logic;
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coutfa_s_o : out std_logic);
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end fulladder_struct;
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architecture structural of fulladder_struct is
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-- Halfadder component
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component halfadder is
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port (a_i : in std_logic;
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b_i : in std_logic;
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sum_o : out std_logic;
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cy_o : out std_logic);
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end component;
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signal sig_ha1e, sig_ha1c, sig_ha2c : std_logic;
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begin
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-- Instances of two halfadders
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HA1: halfadder port map(
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a_i => afa_s_i,
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b_i => bfa_s_i,
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sum_o => sig_ha1e,
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cy_o => sig_ha1c);
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HA2: halfadder port map(
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a_i => sig_ha1e,
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b_i => cinfa_s_i,
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sum_o => sumfa_s_o,
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cy_o => sig_ha2c);
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-- The OR gate
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coutfa_s_o <= sig_ha1c OR sig_ha2c;
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end structural; |