-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;

entity fulladder_struct is
  port (afa_s_i :   in std_logic;
        bfa_s_i :   in std_logic;
        cinfa_s_i :   in std_logic;
        sumfa_s_o : out std_logic;
        coutfa_s_o :  out std_logic);
end fulladder_struct;

architecture structural of fulladder_struct is

-- Halfadder component
component halfadder is
port (a_i :   in std_logic;
      b_i :   in std_logic;
      sum_o : out std_logic;
      cy_o :  out std_logic);
end component;

signal sig_ha1e, sig_ha1c, sig_ha2c : std_logic;

begin

-- Instances of two halfadders
  HA1: halfadder port map(
     a_i => afa_s_i,
     b_i => bfa_s_i,
     sum_o => sig_ha1e,
     cy_o => sig_ha1c);
     
  HA2: halfadder port map(
  	 a_i => sig_ha1e,
     b_i => cinfa_s_i,
     sum_o => sumfa_s_o,
     cy_o => sig_ha2c);

-- The OR gate 
  coutfa_s_o <= sig_ha1c OR sig_ha2c;
     
end structural;