24 lines
309 B
VHDL
24 lines
309 B
VHDL
-- Code your testbench here
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity testbench is
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end testbench;
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architecture tb of testbench is
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component clkGen is
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port (clk : out std_logic);
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end component;
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signal sig_clk : std_logic;
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begin
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DUT: clkGen port map(
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clk => sig_clk
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);
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end tb;
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