-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;


entity testbench is
end testbench;

architecture tb of testbench is

component clkGen is
  port (clk : out std_logic);
end component;

signal sig_clk : std_logic;

begin  
  DUT: clkGen port map(
     clk => sig_clk
  );
 
    
end tb;