39 lines
851 B
VHDL
39 lines
851 B
VHDL
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity testbench is
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end testbench;
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architecture tb of testbench is
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-- DUT component declaration
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component myMux is
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port (sel : in std_logic_vector(1 downto 0);
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data1_i : in std_logic_vector(2 downto 0);
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data2_i : in std_logic_vector(2 downto 0);
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outp : out std_logic_vector(2 downto 0) );
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end component;
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signal sig1, sig2 : std_logic;
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signal sig_sel : std_logic_vector(1 downto 0);
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signal sig_data1, sig_data2, sig_outp : std_logic_vector(2 downto 0);
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begin
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-- DUT instance
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DUT: myMux port map(
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sel => sig_sel,
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data1_i => sig_data1,
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data2_i => sig_data2,
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outp => sig_outp);
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sig_data1 <= "111";
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sig_data2 <= "000";
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sig_sel <= (sig2,sig1);
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sig1 <= '0', '1' after 100 ns, '0' after 200 ns, '1' after 300 ns;
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sig2 <= '0', '1' after 200 ns;
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end tb; |