library IEEE;
use IEEE.std_logic_1164.all;

entity testbench is
end testbench; 


architecture tb of testbench is

-- DUT component declaration
component myMux is
port (sel :   in std_logic_vector(1 downto 0);
        data1_i :   in std_logic_vector(2 downto 0);
        data2_i : in std_logic_vector(2 downto 0);
        outp : out std_logic_vector(2 downto 0) );
end component;

signal sig1, sig2 : std_logic;
signal sig_sel : std_logic_vector(1 downto 0);
signal sig_data1, sig_data2, sig_outp : std_logic_vector(2 downto 0);


begin
-- DUT instance
DUT: myMux port map(
     sel => sig_sel,
     data1_i => sig_data1,
     data2_i => sig_data2,
     outp => sig_outp);
     
sig_data1 <= "111";
sig_data2 <= "000";
sig_sel <= (sig2,sig1);

sig1 <= '0', '1' after 100 ns, '0' after 200 ns, '1' after 300 ns;
sig2 <= '0', '1' after 200 ns;

end tb;