21 lines
472 B
VHDL
21 lines
472 B
VHDL
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity myMux is
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port (sel : in std_logic_vector(1 downto 0);
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data1_i : in std_logic_vector(2 downto 0);
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data2_i : in std_logic_vector(2 downto 0);
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outp : out std_logic_vector(2 downto 0) );
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end myMux;
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architecture behavior of myMux is
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begin
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with sel select outp <= data1_i when "00",
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data2_i when "01",
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"010" when others;
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end behavior;
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