library IEEE;
use IEEE.std_logic_1164.all;


entity myMux is
  port (sel :   in std_logic_vector(1 downto 0);
        data1_i :   in std_logic_vector(2 downto 0);
        data2_i : in std_logic_vector(2 downto 0);
        outp : out std_logic_vector(2 downto 0) );
end myMux;


architecture behavior  of myMux is
  
begin
  with sel select outp <= data1_i when "00",
                          data2_i when "01",
                          "010" when others;
end behavior;