first commit

Task8/.gitignore

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+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

Task8/Task8.vhdpproj

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+<Project>
+  <ItemGroup>
+    <File Include="arithmetic.vhdl" />
+    <File Include="arithmetic_beh.vhdl" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

Task8/arithmetic.vhdl

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+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity arithmetic is
+    port(   I1     :in    std_logic_vector(15-1 downto 0); -- Operand 1
+            I2     :in    std_logic_vector(12-1 downto 0); -- Operand 2
+            O      :out   std_logic_vector(15-1  downto 0); -- Output
+            C      :out   std_logic;                       -- Carry Flag
+            V      :out   std_logic;                       -- Overflow Flag
+            VALID  :out   std_logic                        -- Flag to indicate if the solution is valid or not
+);
+end arithmetic;

Task8/arithmetic_beh.vhdl

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+library IEEE;
+use IEEE.std_logic_1164.all;
+
+architecture behavior of arithmetic is
+
+begin
+
+end behavior;

Task8/vhdl_ls.toml

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+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end