first commit

Task7/.gitignore

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+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

Task7/Task7.vhdpproj

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+<Project>
+  <ItemGroup>
+    <File Include="pwm.vhdl" />
+    <File Include="pwm_beh.vhdl" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

Task7/pwm.vhdl

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+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity pwm is
+    port(   CLK    : in    std_logic;
+            O      : out   std_logic);
+end pwm;     

Task7/pwm_beh.vhdl

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+library IEEE;
+use IEEE.std_logic_1164.all;
+
+architecture behavior of pwm is
+
+    -- Constants for PWM parameters
+    constant CLK_PERIOD : time := 20 ns; -- Assuming 50 MHz clock
+    constant PWM_PERIOD : time := 10 us;  -- Desired period of 10 microseconds
+    constant DUTY_CYCLE : time := 7.2 us;  -- 72% of the period
+
+    -- Signal to store the counter value
+    signal counter : natural range 0 to integer(PWM_PERIOD / CLK_PERIOD) - 1;
+
+begin
+
+    -- Synchronous counter process
+    process(CLK)
+    begin
+        if rising_edge(CLK) then
+            if counter = integer(PWM_PERIOD / CLK_PERIOD) - 1 then
+                counter <= 0;
+            else
+                counter <= counter + 1;
+            end if;
+        end if;
+    end process;
+
+    -- PWM output generation process
+    process(CLK, counter)
+    begin
+        if rising_edge(CLK) then
+            if (CLK_PERIOD * integer(counter)) < DUTY_CYCLE then
+                O <= '1';
+            else
+                O <= '0';
+            end if;
+        end if;
+    end process;
+
+end behavior;

Task7/vhdl_ls.toml

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+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end