first commit

Task6/Task6.vhdpproj

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+<Project>
+  <ItemGroup>
+    <File Include="cache.vhdl" />
+    <File Include="cache_beh.vhdl" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

Task6/cache.vhdl

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+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity cache is
+	port(
+		addr     : in   std_logic_vector(8-1 downto 0);
+		clk      : in   std_logic;
+		en_read  : in   std_logic;
+		data     : out  std_logic_vector(7-1 downto 0);
+		ch_cm    : out  std_logic
+	);
+end cache;

Task6/cache_beh.vhdl

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+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+architecture behavioral of cache is
+    -- Cache parameters
+    constant CACHE_SIZE : integer := 16;
+    constant TAG_WIDTH : integer := 4;
+    constant DATA_WIDTH : integer := 7;
+    constant INDEX_WIDTH : integer := 4;
+
+    -- Cache memory
+    type cache_array is array (0 to CACHE_SIZE-1) of std_logic_vector(TAG_WIDTH+DATA_WIDTH-1 downto 0);
+    constant cache_content : cache_array := (
+        "10001100010", "10000111101", "00111010011", "11001000110",
+        "10001101111", "10001110110", "11011100001", "10111101011",
+        "11101101110", "10001111110", "11010001110", "11011000011",
+        "11111100000", "10101001001", "10000101011", "11101010100"
+    );
+
+    -- Signals
+    signal data_next : std_logic_vector(6 downto 0);
+    signal hit_next : std_logic;
+    
+begin
+    process(clk)
+    begin
+        if falling_edge(clk) then
+            if en_read = '1' then
+                data <= data_next;
+                ch_cm <= hit_next;
+            else
+                data <= "ZZZZZZZ";
+                ch_cm <= '0';
+            end if;
+        end if;
+    end process;
+    
+    process(addr,clk)
+    
+    variable index : integer range 0 to CACHE_SIZE-1;
+    variable tag : std_logic_vector(TAG_WIDTH-1 downto 0);
+    variable cache_tag : std_logic_vector(TAG_WIDTH-1 downto 0);
+    variable cache_data : std_logic_vector(DATA_WIDTH-1 downto 0);
+    
+    begin
+        -- Extract index and tag from address
+        index := to_integer(unsigned(addr(INDEX_WIDTH-1 downto 0)));
+        tag := addr(addr'length-1 downto INDEX_WIDTH);
+        
+        cache_tag := cache_content(index)(TAG_WIDTH+DATA_WIDTH-1 downto DATA_WIDTH);
+        cache_data := cache_content(index)(DATA_WIDTH-1 downto 0);
+
+        if tag = cache_tag then
+            hit_next <= '1'; -- Cache hit
+            data_next <= cache_data;
+        else
+            hit_next <= '0';
+            data_next <= (others => 'Z'); -- Cache miss
+        end if;
+    end process;
+    
+end architecture behavioral;

Task6/vhdl_ls.toml

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+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end