first commit

Task4/.gitignore

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+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

Task4/Task4.vhdpproj

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+<Project>
+  <ItemGroup>
+    <File Include="fsm.vhdl" />
+    <File Include="fsm_beh.vhdl" />
+    <File Include="fsm_pkg.vhdl" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

Task4/fsm.vhdl

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+library IEEE;
+use IEEE.std_logic_1164.all;
+use work.fsm_pkg.all;
+
+entity fsm is
+    port(   
+            CLK     : in    std_logic;
+            INPUT   : in    std_logic_vector(1 downto 0);
+            RST     : in    std_logic;
+            OUTPUT  : out   std_logic_vector(1 downto 0);
+            STATE   : out   fsm_state
+        );
+end fsm;     

Task4/fsm_beh.vhdl

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+library IEEE;
+use IEEE.std_logic_1164.all;
+use work.fsm_pkg.all;
+
+architecture behavior of fsm is
+
+    signal current_state, next_state : work.fsm_pkg.fsm_state;
+    signal next_output : std_logic_vector(1 downto 0);
+
+begin
+    
+    process(CLK, RST)
+    begin
+        if rising_edge(CLK) then
+            if RST = '1' then
+                current_state <= START;
+                OUTPUT <= "00";
+            else
+                current_state <= next_state;
+                OUTPUT <= next_output;
+            end if;
+        end if;
+    end process;
+    
+    process(current_state, INPUT)
+    begin
+        case current_state is
+            when START =>
+                if INPUT = "11" then
+                    next_state <= S2;
+                    next_output <= "00";
+                    
+                else
+                    next_state <= START;
+                    next_output <= "00";
+                    
+                end if;
+                
+            when S0 =>
+                if INPUT = "00" then
+                    next_state <= S2;
+                    next_output <= "00";
+                    
+                elsif INPUT = "10" then
+                    next_state <= S0;
+                    next_output <= "11";
+                    
+                else
+                    next_state <= S0;
+                    next_output <= "00";
+                    
+                end if;
+                
+            when S1 =>
+                if INPUT = "00" then
+                    next_state <= S1;
+                    next_output <= "00";
+                    
+                elsif INPUT = "10" then
+                    next_state <= S2;
+                    next_output <= "10";
+                    
+                else
+                    next_state <= S1;
+                    next_output <= "00";
+                    
+                end if;
+                
+            when S2 =>
+                if INPUT = "00" then
+                    next_state <= S0;
+                    next_output <= "01";
+                    
+                elsif INPUT = "01" then
+                    next_state <= S1;
+                    next_output <= "10";
+                    
+                elsif INPUT = "10" then
+                    next_state <= S2;
+                    next_output <= "11";
+                    
+                else
+                    next_state <= S2;
+                    next_output <= "00";
+                    
+                end if;
+                
+        end case;
+    end process;
+
+    STATE <= current_state;
+
+end behavior;

Task4/fsm_pkg.vhdl

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+package fsm_pkg is
+    type fsm_state is
+    (
+        START,
+        S0,
+        S1,
+        S2
+    );
+end package fsm_pkg;

Task4/vhdl_ls.toml

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+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end