first commit

Task3/.gitignore

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+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

Task3/Task3.vhdpproj

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+<Project>
+  <ItemGroup>
+    <File Include="counter.vhdl" />
+    <File Include="counter_beh.vhdl" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

Task3/counter.vhdl

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+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity counter is
+	port(
+		CLK         : in   std_logic;
+		RST         : in   std_logic;
+		Enable      : in   std_logic;	
+		SyncLoadInput   : in   std_logic;
+		AsyncClear   : in   std_logic;
+		Input       : in   std_logic_vector((6-1) downto 0);	
+		Output      : out  std_logic_vector((6-1) downto 0)
+	);
+end counter;

Task3/counter_beh.vhdl

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+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+architecture behavioral of counter is
+    
+begin
+    process(CLK, RST, AsyncClear)
+    begin
+        if AsyncClear = '1' then
+            Output <= "000000"; -- Asynchrones Löschen
+        elsif rising_edge(CLK) then
+            if RST = '1' then
+                Output <= "000000"; -- Synchroner Reset
+            elsif Enable = '1' then
+                if SyncLoadInput = '1' then
+                    Output <= Input; -- Synchrones Laden
+                else
+                    Output <= std_logic_vector(unsigned(Output) + 1); -- Inkrement
+                end if;
+            end if;
+        end if;
+    end process;
+end behavioral;

Task3/vhdl_ls.toml

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+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end