first commit

Task2/.gitignore

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+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

Task2/Task2.vhdpproj

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+<Project>
+  <ItemGroup>
+    <File Include="demux.vhdl" />
+    <File Include="demux_beh.vhdl" />
+    <File Include="desc_7_Task2.pdf" />
+  </ItemGroup>
+  <PropertyGroup>
+    <HardwareStartPath>Task2.vhd</HardwareStartPath>
+  </PropertyGroup>
+</Project>

Task2/demux.vhdl

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+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity demux is
+    port ( IN1  : in  std_logic_vector((4 - 1) downto 0);
+           SEL  : in  std_logic_vector((3 - 1) downto 0);
+           OUT1 : out std_logic_vector((4 - 1) downto 0);
+           OUT2 : out std_logic_vector((4 - 1) downto 0);
+           OUT3 : out std_logic_vector((4 - 1) downto 0);
+           OUT4 : out std_logic_vector((4 - 1) downto 0);
+           OUT5 : out std_logic_vector((4 - 1) downto 0));
+
+end demux;

Task2/demux_beh.vhdl

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+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+architecture behavior of demux is
+    
+    CONSTANT O1 : std_logic_vector(0 to 2)     := "000";
+    CONSTANT O2 : std_logic_vector(0 to 2)     := "001";
+    CONSTANT O3 : std_logic_vector(0 to 2)     := "010";
+    CONSTANT O4 : std_logic_vector(0 to 2)     := "011";
+    CONSTANT O5 : std_logic_vector(0 to 2)     := "100";
+    CONSTANT OE : std_logic_vector(0 to 3)     := "0000";
+    
+begin
+    process(SEL, IN1)
+    begin
+        case SEL is
+            when O1 =>
+                OUT1 <= IN1;
+                OUT2 <= OE;
+                OUT3 <= OE;
+                OUT4 <= OE;
+                OUT5 <= OE;
+            when O2 =>
+                OUT1 <= OE;
+                OUT2 <= IN1;
+                OUT3 <= OE;
+                OUT4 <= OE;
+                OUT5 <= OE;
+            when O3 =>   OUT3 <= IN1;
+                OUT1 <= OE;
+                OUT2 <= OE;
+                OUT3 <= IN1;
+                OUT4 <= OE;
+                OUT5 <= OE;
+            when O4 =>   OUT4 <= IN1;
+                OUT1 <= OE;
+                OUT2 <= OE;
+                OUT3 <= OE;
+                OUT4 <= IN1;
+                OUT5 <= OE;
+            when O5 =>   OUT5 <= IN1;
+                OUT1 <= OE;
+                OUT2 <= OE;
+                OUT3 <= OE;
+                OUT4 <= OE;
+                OUT5 <= IN1;
+            when others =>
+                OUT1 <= OE;
+                OUT2 <= OE;
+                OUT3 <= OE;
+                OUT4 <= OE;
+                OUT5 <= OE;
+        end case;
+    end process;
+end behavior;

Task2/vhdl_ls.toml

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+# auto-generated
+[Libraries]
+work.files = [
+	'Task2.vhd',
+	'Task2_tb.vhd'
+]
+[libraries.work]
+files = [
+	'Task2.vhd',
+	'Task2_tb.vhd'
+]
+# auto-generated-end