first commit

19_RAMbus_Example/.gitignore

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+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

19_RAMbus_Example/19_RAMbus_Example.vhdpproj

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+<Project>
+  <ItemGroup>
+    <File Include="clkgen.vhd" />
+    <File Include="design.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

19_RAMbus_Example/clkgen.vhd

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+-- Clock Generator
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity clkGen is
+  port (clk : out std_logic);
+end clkGen;
+
+architecture behavior of clkGen is
+
+constant clk_period : time := 10 ns;
+
+begin
+  clkgen : process
+  
+  begin
+  
+  	clk <= '0';
+    wait for clk_period/2;  
+    clk <= '1';
+    wait for clk_period/2;  
+  end process clkgen;
+end behavior;

19_RAMbus_Example/design.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity single_port_ram is
+	port
+	(
+		data	: inout std_logic_vector(7 downto 0);
+        addr	: in std_logic_vector(15 downto 0);
+        cs		: in std_logic; -- chip select
+		we		: in std_logic; -- write enable
+        oe		: in std_logic; -- output enable
+		clk		: in std_logic
+	);
+	
+end entity;
+
+architecture rtl of single_port_ram is
+
+	-- Build a 2-D array type for the RAM
+	subtype word_t is std_logic_vector(7 downto 0);
+	type memory_t is array(127 downto 0) of word_t;
+	
+	signal ram : memory_t;
+	
+begin
+
+
+wr: process (clk) begin
+        if (rising_edge(clk)) then
+            if ( cs = '1' and we = '1') then             -- write (= ram stores data from data input) when we = 1
+                ram(to_integer(unsigned(addr))) <= data;
+            end if;
+        end if;
+    end process;
+    
+rd: process (clk) begin
+        if (rising_edge(clk)) then
+            if (cs = '1' and we = '0' and oe = '1') then  -- read (= ram provides data at data ouput) only when we = 0 and oe = 1
+                data <= ram(to_integer(unsigned(addr)));
+            else
+                data <= (others=>'Z'); -- IMPORTANT
+            end if;
+        end if;
+    end process;    
+    
+end rtl;

19_RAMbus_Example/testbench.vhd

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+-- Code your testbench here
+library IEEE;
+use IEEE.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity testbench is
+end testbench;
+
+architecture tb of testbench is
+
+component single_port_ram is
+port
+	(
+		data	: inout std_logic_vector(7 downto 0);
+        addr	: in std_logic_vector(15 downto 0);
+		cs		: in std_logic;
+		we		: in std_logic;
+        oe		: in std_logic;
+		clk		: in std_logic
+	);
+end component;
+
+component clkGen is
+  port (clk : out std_logic);
+end component;
+
+signal sig_clk : std_logic;
+signal sig_addr : std_logic_vector(15 downto 0);
+signal sig_data : std_logic_vector(7 downto 0);
+signal sig_we : std_logic;
+signal sig_cs : std_logic;
+signal sig_oe : std_logic;
+
+
+
+begin  
+  DUT: single_port_ram port map(
+     clk => sig_clk,
+     addr => sig_addr,
+     data => sig_data,
+     we => sig_we,
+     cs => sig_cs,
+     oe => sig_oe
+  );
+  
+  mClkGen : clkGen port map(
+  	clk => sig_clk
+  );
+
+stim: process 
+
+ procedure ReadRAM(read_addr : in integer) is
+    begin
+    sig_data <= (others => 'Z');
+    sig_we <= '0';
+    sig_oe <= '1';
+    sig_cs <= '1';
+    sig_addr <= std_logic_vector(to_unsigned(read_addr,16));
+ end procedure ReadRAM;
+ 
+ procedure WriteRAM(write_addr : in integer; write_data : in std_logic_vector(7 downto 0)) is
+    begin
+    sig_we <= '1';
+    sig_oe <= '0';
+    sig_cs <= '1';
+    sig_addr <= std_logic_vector(to_unsigned(write_addr,16));
+    sig_data <= write_data;
+ end procedure WriteRAM;
+   
+   
+begin
+
+wait for 7 ns;
+
+WriteRAM(2,"00000001");
+wait for 20 ns;
+WriteRAM(4,"00000010");
+wait for 20 ns;
+WriteRAM(6,"00000011");
+wait for 20 ns;
+WriteRAM(8,"00000100");
+wait for 20 ns;
+WriteRAM(10,"11111111");
+wait for 20 ns;
+
+ReadRAM(2);
+wait for 20 ns;
+ReadRAM(4);
+wait for 20 ns;
+ReadRAM(6);
+wait for 20 ns;
+ReadRAM(8);
+wait for 20 ns;
+ReadRAM(10);
+wait for 20 ns;
+ReadRAM(11);
+wait for 20 ns;
+
+
+wait;
+end process stim;
+
+
+end tb;

19_RAMbus_Example/vhdl_ls.toml

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+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end