first commit

18_RAM_Example/.gitignore

@@ -0,0 +1,40 @@
+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

18_RAM_Example/18_RAM_Example.vhdpproj

@@ -0,0 +1,8 @@
+<Project>
+  <ItemGroup>
+    <File Include="clkgen.vhd" />
+    <File Include="design.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

18_RAM_Example/clkgen.vhd

@@ -0,0 +1,24 @@
+-- Clock Generator
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity clkGen is
+  port (clk : out std_logic);
+end clkGen;
+
+architecture behavior of clkGen is
+
+constant clk_period : time := 10 ns;
+
+begin
+  clkgen : process
+  
+  begin
+  
+  	clk <= '0';
+    wait for clk_period/2;  
+    clk <= '1';
+    wait for clk_period/2;  
+  end process clkgen;
+end behavior;

18_RAM_Example/design.vhd

@@ -0,0 +1,46 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity single_port_ram is
+	port
+	(
+		data	: in std_logic_vector(7 downto 0);
+        addr	: in std_logic_vector(15 downto 0);
+		we		: in std_logic;
+		clk		: in std_logic;
+		q		: out std_logic_vector(7 downto 0)
+	);
+	
+end entity;
+
+architecture rtl of single_port_ram is
+
+	-- Build a 2-D array type for the RAM
+	subtype word_t is std_logic_vector(7 downto 0);
+	type memory_t is array(2**7-1 downto 0) of word_t; -- 2**7 = 128
+	
+	signal ram : memory_t;
+	
+	-- Register to hold the address
+	signal addr_reg : std_logic_vector(15 downto 0);
+
+begin
+
+	process(clk)
+	begin
+		if(rising_edge(clk)) then
+			if(we = '1') then
+				ram(to_integer(unsigned(addr))) <= data;       
+			end if;
+			
+			-- Register the address for reading (synchron)
+			addr_reg <= addr;
+		end if;
+	
+	end process;
+	
+    -- asynchron data output (but attention: addr_reg changes synchronously)
+	q <= ram(to_integer(unsigned(addr_reg)));
+	
+end rtl;

18_RAM_Example/testbench.vhd

@@ -0,0 +1,95 @@
+-- Code your testbench here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity testbench is
+end testbench;
+
+architecture tb of testbench is
+
+component single_port_ram is
+port
+	(
+		data	: in std_logic_vector(7 downto 0);
+        addr	: in std_logic_vector(15 downto 0);
+		we		: in std_logic;
+		clk		: in std_logic;
+		q		: out std_logic_vector(7 downto 0)
+	);
+end component;
+
+component clkGen is
+  port (clk : out std_logic);
+end component;
+
+signal sig_clk : std_logic;
+signal sig_addr : std_logic_vector(15 downto 0);
+signal sig_q : std_logic_vector(7 downto 0);
+signal sig_data : std_logic_vector(7 downto 0);
+signal sig_we : std_logic;
+use ieee.numeric_std.all;
+
+begin  
+  DUT: single_port_ram port map(
+     clk => sig_clk,
+     addr => sig_addr,
+     data => sig_data,
+     we => sig_we,
+     q => sig_q
+  );
+  
+  mClkGen : clkGen port map(
+  	clk => sig_clk
+  );
+
+stim: process 
+
+ procedure ReadRAM(read_addr : in integer) is
+    begin
+    sig_we <= '0';
+    sig_addr <= std_logic_vector(to_unsigned(read_addr,16));
+ end procedure ReadRAM;
+ 
+ procedure WriteRAM(write_addr : in integer; write_data : in std_logic_vector(7 downto 0)) is
+    begin
+    sig_we <= '1';
+    sig_addr <= std_logic_vector(to_unsigned(write_addr,16));
+    sig_data <= write_data;
+ end procedure WriteRAM;
+   
+   
+begin
+
+wait for 7 ns;
+
+WriteRAM(2,"00000001");
+wait for 20 ns;
+WriteRAM(4,"00000010");
+wait for 20 ns;
+WriteRAM(6,"00000011");
+wait for 20 ns;
+WriteRAM(8,"00000100");
+wait for 20 ns;
+WriteRAM(10,"11111111");
+wait for 30 ns;
+
+ReadRAM(2);
+wait for 20 ns;
+ReadRAM(4);
+wait for 20 ns;
+ReadRAM(6);
+wait for 20 ns;
+ReadRAM(8);
+wait for 20 ns;
+ReadRAM(10);
+wait for 20 ns;
+ReadRAM(11);
+wait for 20 ns;
+
+
+wait;
+end process stim;
+
+
+end tb;

18_RAM_Example/vhdl_ls.toml

@@ -0,0 +1,8 @@
+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end