first commit

16_asyncROM_Example/.gitignore

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+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

16_asyncROM_Example/16_asyncROM_Example.vhdpproj

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+<Project>
+  <ItemGroup>
+    <File Include="design.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup>
+    <HardwareStartPath>testbench.vhd</HardwareStartPath>
+  </PropertyGroup>
+</Project>

16_asyncROM_Example/design.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity single_port_rom is
+    port
+    (
+        addr    : in std_logic_vector(3 downto 0);
+        q        : out std_logic_vector(4 downto 0)
+    );
+end single_port_rom;
+    
+architecture rtl of single_port_rom is
+
+    -- Build a 2-D array type for the ROM
+    subtype word_t is std_logic_vector(4 downto 0);
+    type memory_t is array(0 to 15) of word_t;
+        
+    constant romdata : memory_t := (
+     "10101",                            -- data for address 0
+     "11111",                            -- data for address 1
+     "10101",
+     "11110",
+     "10110",
+     "10101",
+     "11010",
+     "10010",
+     "10110",
+     "11101",
+     "10110",
+     "10111",
+     "00110",
+     "11101",
+     "10010",
+     "10110"                             -- data for address 15
+     );
+          
+begin
+        q <= romdata(to_integer(unsigned(addr)));
+        
+end rtl;

16_asyncROM_Example/testbench.vhd

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+-- Code your testbench here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity testbench is
+end testbench;
+
+architecture tb of testbench is
+
+component single_port_rom is
+port
+    (
+        addr    : in std_logic_vector(3 downto 0);
+        q        : out std_logic_vector(4 downto 0)
+    );
+end component;
+
+
+signal sig_addr : std_logic_vector(3 downto 0);
+signal sig_q : std_logic_vector(4 downto 0);
+
+
+begin  
+  DUT: single_port_rom port map(
+     addr => sig_addr,
+     q => sig_q
+  );
+  
+
+
+stim: process 
+begin
+sig_addr <= "0000";
+wait for 10 ns;
+sig_addr <= "0001";
+wait for 10 ns;
+sig_addr <= "0010";
+wait for 10 ns;
+sig_addr <= "0100";
+wait for 10 ns;
+sig_addr <= "1000";
+wait;
+end process stim;
+
+
+end tb;

16_asyncROM_Example/vhdl_ls.toml

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+# auto-generated
+[Libraries]
+work.files = [
+	'design.vhd',
+	'testbench.vhd'
+]
+[libraries.work]
+files = [
+	'design.vhd',
+	'testbench.vhd'
+]
+# auto-generated-end