first commit

11_MinArith/.gitignore

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+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

11_MinArith/11_MinArith.vhdpproj

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+<Project>
+  <ItemGroup>
+    <File Include="design.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

11_MinArith/design.vhd

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+library IEEE;
+use IEEE.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity minArith is
+  port (a_i :   in std_logic_vector (7 downto 0);
+        b_i :   in std_logic_vector (7 downto 0);
+        ssum_o : out std_logic_vector (7 downto 0);
+        sdiff_o :  out std_logic_vector (7 downto 0);
+        usum_o : out std_logic_vector (7 downto 0);
+        udiff_o :  out std_logic_vector (7 downto 0);
+        ainc_o :  out std_logic_vector (7 downto 0));
+end minArith;
+
+-- behavioral description of the halfadder given by two gates
+architecture behavior of minArith is
+begin
+  ssum_o  <= std_logic_vector(signed(a_i)   + signed(b_i));
+  sdiff_o <= std_logic_vector(signed(a_i)   - signed(b_i));
+  usum_o  <= std_logic_vector(unsigned(a_i) + unsigned(b_i));
+  udiff_o <= std_logic_vector(unsigned(a_i) - unsigned(b_i));
+  ainc_o  <= std_logic_vector(unsigned(a_i) + "00000001");
+  
+end behavior;

11_MinArith/testbench.vhd

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+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity testbench is
+end testbench; 
+
+
+architecture tb of testbench is
+
+component minArith is
+port (a_i :   in std_logic_vector (7 downto 0);
+      b_i :   in std_logic_vector (7 downto 0);
+      ssum_o : out std_logic_vector (7 downto 0);
+      sdiff_o :  out std_logic_vector (7 downto 0);
+      usum_o : out std_logic_vector (7 downto 0);
+      udiff_o :  out std_logic_vector (7 downto 0);
+      ainc_o :  out std_logic_vector (7 downto 0));
+end component;
+
+
+signal sig_a, sig_b, sig_ssum, sig_sdiff, sig_usum, sig_udiff, sig_ainc : std_logic_vector(7 downto 0);
+
+begin
+
+  DUT: minArith port map(
+      a_i => sig_a,
+      b_i => sig_b,
+      ssum_o => sig_ssum,
+      sdiff_o => sig_sdiff,
+      usum_o => sig_usum,
+      udiff_o => sig_udiff,
+      ainc_o => sig_ainc );
+
+  
+  
+  sig_a <= "00000001", "00000010" after 100 ns, "00001010" after 200 ns;
+  sig_b <= "00000001", "00000011" after 100 ns, "00100010" after 200 ns;
+
+end tb;

11_MinArith/vhdl_ls.toml

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+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end