first commit

08_InfereredLatch_Example/.gitignore

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+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

08_InfereredLatch_Example/08_InfereredLatch_Example.vhdpproj

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+<Project>
+  <ItemGroup>
+    <File Include="design.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

08_InfereredLatch_Example/design.vhd

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+-- Code your design here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity InfLatch is 
+port ( D:in std_logic;
+       En:in std_logic;
+       Q:out std_logic);
+end InfLatch;
+
+architecture beh of InfLatch is
+begin
+
+p0: process (D,En)
+begin
+ if En= '1' then
+ Q <= D;
+ end if;
+end process p0;
+
+end beh;

08_InfereredLatch_Example/testbench.vhd

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+-- Code your testbench here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity testbench is
+-- empty
+end testbench;
+
+architecture tb of testbench is
+
+component InfLatch is
+port ( D:in std_logic;
+       En:in std_logic;
+       Q:out std_logic);
+end component;
+
+signal sig_D, sig_En, sig_Q : std_logic;
+
+begin  
+  DUT: InfLatch port map(
+     D => sig_D,
+     En => sig_en,
+     Q => sig_Q
+  );
+  
+stim : process 
+begin 
+ sig_D <= '1';
+ sig_EN <= '0';
+ wait for 10 ns;
+ sig_En <= '1';
+ wait for 2 ns;
+ sig_D <= '0';
+ wait for 2 ns;
+ sig_D <= '1';
+ wait for 10 ns;
+ sig_En <= '0';
+ wait for 2 ns;
+ sig_D <= '0';
+ wait for 2 ns;
+ sig_D <= '1';
+ wait;
+end process stim;
+
+end tb;

08_InfereredLatch_Example/vhdl_ls.toml

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+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end