first commit

06_VELS_Example/.gitignore

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+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

06_VELS_Example/06_VELS_Example.vhdpproj

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+<Project>
+  <ItemGroup>
+    <File Include="design.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

06_VELS_Example/design.vhd

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+-- be aware of the correct order!
+-- EDA compiles from left to right
+
+-- 1) gate entities 
+-- 2) architectures for the gate entities
+-- 3) Package (must be done after 1, because otherwise componante is not known)
+-- 4) your entity
+-- 5) your architecture (needs to know all above)
+-- 6) Testbench Entity
+-- 7) Testbench Architecture (in same file as testbench entity)
+
+
+-- This example is related to the first VELS taks using packages (if there is no package, skip step 1-3)

06_VELS_Example/testbench.vhd

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+library IEEE;
+use IEEE.std_logic_1164.all;
+--use IEEE.std_artih.all;
+
+
+entity testbench is
+end testbench; 
+
+
+architecture tb of testbench is
+
+  -- declare your DUT
+  component gates is
+      port(   A,B,C,D : in    std_logic;
+              O       : out   std_logic);
+  end component;
+
+
+  -- needed signals
+  signal sig_A, sig_B, sig_C, sig_D, sig_O: std_logic;
+
+  begin
+
+    -- Connect DUT with tb signals
+    DUT: gates port map(
+       A => sig_A,
+       B => sig_B,
+       C => sig_C,
+       D => sig_D,
+       O => sig_O);
+
+    -- define process for testing our DUT
+    gate_tester : process
+
+     -- define a procedure (Slides 07) that applys input vector, waits and than checks output
+      procedure check_sample(val_A, val_B, val_C, val_D, val_O : in std_logic) is
+      begin
+
+		-- apply signals to DUT inputs
+        sig_A <= val_A;
+        sig_B <= val_B;
+        sig_C <= val_C;
+        sig_D <= val_D;
+
+		-- wait (at least 1 delta cycle)
+        wait for 10 ns;
+
+		-- check output of DUT and report possible error message
+        assert (sig_O = val_O) report "Error for A= " 
+        & std_logic'image(val_A) & " B= "  
+        & std_logic'image(val_B) & " C= " 
+        & std_logic'image(val_C) & " D= " 
+        & std_logic'image(val_D) & ". Output is "
+        & std_logic'image(sig_O)  & " but should be " 
+        & std_logic'image(val_O)  & "."
+        severity failure; 
+
+      end procedure check_sample;
+
+    begin
+
+      -- now use procedure to check different combinations
+      -- change this according to your solution
+      -- (can also be done with loop, but we havn't learned that yet)
+      check_sample('0','0','0','0','1');
+      check_sample('0','0','0','1','0');
+      check_sample('1','1','1','1','1');
+
+	  -- wait forever to stop process
+      wait;
+
+    end process gate_tester;
+
+end tb;

06_VELS_Example/vhdl_ls.toml

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+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end