first commit

04_ClockGen_Example/.gitignore

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+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

04_ClockGen_Example/04_ClockGen_Example.vhdpproj

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+<Project>
+  <ItemGroup>
+    <File Include="clkGen.vhd" />
+    <File Include="design.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup>
+    <HardwareStartPath>testbench.vhd</HardwareStartPath>
+  </PropertyGroup>
+</Project>

04_ClockGen_Example/clkGen.vhd

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+-- Clock Generator
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity clkGen is
+  port (clk : out std_logic);
+end clkGen;
+
+architecture behavior of clkGen is
+
+constant clk_period : time := 10 ns;
+
+begin
+  clkgen : process
+  
+  begin
+  
+  	clk <= '0';
+    wait for clk_period/2;  
+    clk <= '1';
+    wait for clk_period/2;  
+  end process clkgen;
+end behavior;

04_ClockGen_Example/testbench.vhd

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+-- Code your testbench here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity testbench is
+end testbench;
+
+architecture tb of testbench is
+
+component clkGen is
+  port (clk : out std_logic);
+end component;
+
+signal sig_clk : std_logic;
+
+begin  
+  DUT: clkGen port map(
+     clk => sig_clk
+  );
+ 
+    
+end tb;

04_ClockGen_Example/vhdl_ls.toml

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+# auto-generated
+[Libraries]
+work.files = [
+	'clkGen.vhd',
+	'design.vhd',
+	'testbench.vhd'
+]
+[libraries.work]
+files = [
+	'clkGen.vhd',
+	'design.vhd',
+	'testbench.vhd'
+]
+# auto-generated-end