first commit

03_MUX_Example/.gitignore

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+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

03_MUX_Example/03_MUX_Example.vhdpproj

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+<Project>
+  <ItemGroup>
+    <File Include="design.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

03_MUX_Example/design.vhd

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+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity myMux is
+  port (sel :   in std_logic_vector(1 downto 0);
+        data1_i :   in std_logic_vector(2 downto 0);
+        data2_i : in std_logic_vector(2 downto 0);
+        outp : out std_logic_vector(2 downto 0) );
+end myMux;
+
+
+architecture behavior  of myMux is
+  
+begin
+  with sel select outp <= data1_i when "00",
+                          data2_i when "01",
+                          "010" when others;
+end behavior;

03_MUX_Example/testbench.vhd

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+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity testbench is
+end testbench; 
+
+
+architecture tb of testbench is
+
+-- DUT component declaration
+component myMux is
+port (sel :   in std_logic_vector(1 downto 0);
+        data1_i :   in std_logic_vector(2 downto 0);
+        data2_i : in std_logic_vector(2 downto 0);
+        outp : out std_logic_vector(2 downto 0) );
+end component;
+
+signal sig1, sig2 : std_logic;
+signal sig_sel : std_logic_vector(1 downto 0);
+signal sig_data1, sig_data2, sig_outp : std_logic_vector(2 downto 0);
+
+
+begin
+-- DUT instance
+DUT: myMux port map(
+     sel => sig_sel,
+     data1_i => sig_data1,
+     data2_i => sig_data2,
+     outp => sig_outp);
+     
+sig_data1 <= "111";
+sig_data2 <= "000";
+sig_sel <= (sig2,sig1);
+
+sig1 <= '0', '1' after 100 ns, '0' after 200 ns, '1' after 300 ns;
+sig2 <= '0', '1' after 200 ns;
+
+end tb;

03_MUX_Example/vhdl_ls.toml

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+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end