12 lines
557 B
VHDL
12 lines
557 B
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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entity arithmetic is
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port( I1 :in std_logic_vector(15-1 downto 0); -- Operand 1
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I2 :in std_logic_vector(12-1 downto 0); -- Operand 2
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O :out std_logic_vector(15-1 downto 0); -- Output
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C :out std_logic; -- Carry Flag
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V :out std_logic; -- Overflow Flag
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VALID :out std_logic -- Flag to indicate if the solution is valid or not
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);
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end arithmetic; |