63 lines
2.0 KiB
VHDL
63 lines
2.0 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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architecture behavioral of cache is
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-- Cache parameters
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constant CACHE_SIZE : integer := 16;
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constant TAG_WIDTH : integer := 4;
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constant DATA_WIDTH : integer := 7;
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constant INDEX_WIDTH : integer := 4;
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-- Cache memory
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type cache_array is array (0 to CACHE_SIZE-1) of std_logic_vector(TAG_WIDTH+DATA_WIDTH-1 downto 0);
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constant cache_content : cache_array := (
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"10001100010", "10000111101", "00111010011", "11001000110",
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"10001101111", "10001110110", "11011100001", "10111101011",
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"11101101110", "10001111110", "11010001110", "11011000011",
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"11111100000", "10101001001", "10000101011", "11101010100"
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);
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-- Signals
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signal data_next : std_logic_vector(6 downto 0);
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signal hit_next : std_logic;
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begin
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process(clk)
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begin
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if falling_edge(clk) then
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if en_read = '1' then
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data <= data_next;
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ch_cm <= hit_next;
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else
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data <= "ZZZZZZZ";
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ch_cm <= '0';
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end if;
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end if;
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end process;
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process(addr,clk)
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variable index : integer range 0 to CACHE_SIZE-1;
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variable tag : std_logic_vector(TAG_WIDTH-1 downto 0);
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variable cache_tag : std_logic_vector(TAG_WIDTH-1 downto 0);
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variable cache_data : std_logic_vector(DATA_WIDTH-1 downto 0);
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begin
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-- Extract index and tag from address
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index := to_integer(unsigned(addr(INDEX_WIDTH-1 downto 0)));
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tag := addr(addr'length-1 downto INDEX_WIDTH);
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cache_tag := cache_content(index)(TAG_WIDTH+DATA_WIDTH-1 downto DATA_WIDTH);
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cache_data := cache_content(index)(DATA_WIDTH-1 downto 0);
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if tag = cache_tag then
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hit_next <= '1'; -- Cache hit
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data_next <= cache_data;
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else
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hit_next <= '0';
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data_next <= (others => 'Z'); -- Cache miss
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end if;
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end process;
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end architecture behavioral; |