13 lines
293 B
VHDL
13 lines
293 B
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity cache is
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port(
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addr : in std_logic_vector(8-1 downto 0);
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clk : in std_logic;
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en_read : in std_logic;
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data : out std_logic_vector(7-1 downto 0);
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ch_cm : out std_logic
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);
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end cache; |