60 lines
2.2 KiB
VHDL
60 lines
2.2 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.Numeric_Std.all;
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architecture Behavioral of RAM is
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-- Die Länge der Adressen beträgt 6 Bit -> Länge/Größe des Vektors 64
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-- die Länge der einzelnen Speicherzellen 8 Bit
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type memory_type is array (0 to 127) of std_logic_vector(17 downto 0);
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-- Der anfängliche Inhalt des Speichers ist Null.
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signal memory : memory_type := (others => (others => '0'));
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--constant for high Z
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constant high_z : std_logic_vector(35 downto 0) := "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
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begin
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process (Clk) is
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variable addr1_int : INTEGER;
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variable addr2_int : INTEGER;
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begin
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if rising_edge(Clk) then
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output1 <= high_z;
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output2 <= high_z;
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addr1_int := to_integer(UNSIGNED(addr1));
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addr2_int := to_integer(UNSIGNED(addr2));
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if en_write = '0' then
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-- lesen
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if en_read1 = '1' then
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output1 <= memory(addr1_int+1) & memory(addr1_int);
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end if;
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if en_read2 = '1' then
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output2 <= memory(addr2_int+1) & memory(addr2_int);
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end if;
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--high Z wenn nur eins gelesen wird:
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if (en_read2 = '0') and (en_read1 = '1') then
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output2 <= high_z;
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elsif (en_read1 = '0') and (en_read2 = '1') then
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output1 <= high_z;
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end if;
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end if;
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-- schreiben
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if (en_write = '1') and (en_read1 = '0') and (en_read2 = '0') then
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memory(addr1_int) <= input;
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-- schreiben und lesen von addr2
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elsif (en_write = '1') and (en_read1 = '0') and (en_read2 = '1') then
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--kann nur ausgeführ werden wenn addr1 != addr2
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if not(addr1_int = addr2_int) and not(addr1_int = addr2_int+1) then
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memory(addr1_int) <= input;
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output2 <= memory(addr2_int+1) & memory(addr2_int);
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end if;
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end if;
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end if;
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end process;
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end Behavioral; |