93 lines
2.5 KiB
VHDL
93 lines
2.5 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use work.fsm_pkg.all;
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architecture behavior of fsm is
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signal current_state, next_state : work.fsm_pkg.fsm_state;
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signal next_output : std_logic_vector(1 downto 0);
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begin
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process(CLK, RST)
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begin
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if rising_edge(CLK) then
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if RST = '1' then
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current_state <= START;
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OUTPUT <= "00";
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else
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current_state <= next_state;
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OUTPUT <= next_output;
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end if;
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end if;
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end process;
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process(current_state, INPUT)
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begin
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case current_state is
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when START =>
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if INPUT = "11" then
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next_state <= S2;
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next_output <= "00";
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else
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next_state <= START;
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next_output <= "00";
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end if;
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when S0 =>
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if INPUT = "00" then
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next_state <= S2;
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next_output <= "00";
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elsif INPUT = "10" then
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next_state <= S0;
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next_output <= "11";
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else
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next_state <= S0;
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next_output <= "00";
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end if;
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when S1 =>
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if INPUT = "00" then
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next_state <= S1;
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next_output <= "00";
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elsif INPUT = "10" then
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next_state <= S2;
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next_output <= "10";
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else
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next_state <= S1;
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next_output <= "00";
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end if;
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when S2 =>
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if INPUT = "00" then
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next_state <= S0;
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next_output <= "01";
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elsif INPUT = "01" then
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next_state <= S1;
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next_output <= "10";
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elsif INPUT = "10" then
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next_state <= S2;
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next_output <= "11";
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else
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next_state <= S2;
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next_output <= "00";
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end if;
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end case;
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end process;
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STATE <= current_state;
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end behavior; |