14 lines
350 B
VHDL
14 lines
350 B
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use work.fsm_pkg.all;
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entity fsm is
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port(
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CLK : in std_logic;
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INPUT : in std_logic_vector(1 downto 0);
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RST : in std_logic;
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OUTPUT : out std_logic_vector(1 downto 0);
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STATE : out fsm_state
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);
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end fsm;
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