15 lines
387 B
VHDL
15 lines
387 B
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity counter is
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port(
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CLK : in std_logic;
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RST : in std_logic;
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Enable : in std_logic;
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SyncLoadInput : in std_logic;
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AsyncClear : in std_logic;
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Input : in std_logic_vector((6-1) downto 0);
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Output : out std_logic_vector((6-1) downto 0)
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);
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end counter; |