56 lines
1.6 KiB
VHDL
56 lines
1.6 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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architecture behavior of demux is
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CONSTANT O1 : std_logic_vector(0 to 2) := "000";
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CONSTANT O2 : std_logic_vector(0 to 2) := "001";
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CONSTANT O3 : std_logic_vector(0 to 2) := "010";
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CONSTANT O4 : std_logic_vector(0 to 2) := "011";
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CONSTANT O5 : std_logic_vector(0 to 2) := "100";
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CONSTANT OE : std_logic_vector(0 to 3) := "0000";
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begin
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process(SEL, IN1)
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begin
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case SEL is
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when O1 =>
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OUT1 <= IN1;
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OUT2 <= OE;
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OUT3 <= OE;
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OUT4 <= OE;
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OUT5 <= OE;
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when O2 =>
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OUT1 <= OE;
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OUT2 <= IN1;
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OUT3 <= OE;
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OUT4 <= OE;
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OUT5 <= OE;
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when O3 => OUT3 <= IN1;
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OUT1 <= OE;
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OUT2 <= OE;
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OUT3 <= IN1;
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OUT4 <= OE;
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OUT5 <= OE;
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when O4 => OUT4 <= IN1;
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OUT1 <= OE;
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OUT2 <= OE;
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OUT3 <= OE;
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OUT4 <= IN1;
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OUT5 <= OE;
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when O5 => OUT5 <= IN1;
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OUT1 <= OE;
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OUT2 <= OE;
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OUT3 <= OE;
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OUT4 <= OE;
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OUT5 <= IN1;
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when others =>
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OUT1 <= OE;
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OUT2 <= OE;
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OUT3 <= OE;
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OUT4 <= OE;
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OUT5 <= OE;
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end case;
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end process;
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end behavior; |