13 lines
478 B
VHDL
13 lines
478 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity demux is
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port ( IN1 : in std_logic_vector((4 - 1) downto 0);
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SEL : in std_logic_vector((3 - 1) downto 0);
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OUT1 : out std_logic_vector((4 - 1) downto 0);
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OUT2 : out std_logic_vector((4 - 1) downto 0);
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OUT3 : out std_logic_vector((4 - 1) downto 0);
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OUT4 : out std_logic_vector((4 - 1) downto 0);
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OUT5 : out std_logic_vector((4 - 1) downto 0));
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end demux; |