44 lines
764 B
VHDL
44 lines
764 B
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use work.IEEE_1164_Gates_pkg.all;
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architecture behavior of gates is
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signal sig_g0, sig_g1, sig_g2, sig_g3 : std_logic;
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begin
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G3: OR3 port map(
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I1 => A,
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I2 => not(B),
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I3 => C,
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O => sig_g3);
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G2: XOR3 port map(
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I1 => not(B),
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I2 => C,
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I3 => not(D),
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O => sig_g2);
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G1: OR3 port map(
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I1 => A,
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I2 => C,
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I3 => not(D),
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O => sig_g1);
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G0: AND3 port map(
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I1 => not(A),
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I2 => B,
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I3 => C,
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O => sig_g0);
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G4: OR4 port map(
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I1 => sig_g3,
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I2 => not(sig_g2),
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I3 => sig_g1,
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I4 => sig_g0,
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O => O);
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end behavior;
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