87 lines
2.3 KiB
VHDL
87 lines
2.3 KiB
VHDL
-- Code your testbench here
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity testbench is
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end testbench;
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architecture tb of testbench is
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component ram_dp is
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port (
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clk :in std_logic;
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address_0 :in std_logic_vector (8-1 downto 0);
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data_0 :inout std_logic_vector (8-1 downto 0);
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cs_0 :in std_logic;
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we_0 :in std_logic;
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oe_0 :in std_logic;
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address_1 :in std_logic_vector (8-1 downto 0);
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data_1 :inout std_logic_vector (8-1 downto 0);
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cs_1 :in std_logic;
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we_1 :in std_logic;
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oe_1 :in std_logic
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);
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end component;
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component clkGen is
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port (clk : out std_logic);
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end component;
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signal sig_clk : std_logic;
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signal sig_address_0 : std_logic_vector (8-1 downto 0);
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signal sig_data_0 : std_logic_vector (8-1 downto 0);
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signal sig_cs_0 : std_logic;
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signal sig_we_0 : std_logic;
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signal sig_oe_0 : std_logic;
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signal sig_address_1 : std_logic_vector (8-1 downto 0);
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signal sig_data_1 : std_logic_vector (8-1 downto 0);
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signal sig_cs_1 : std_logic;
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signal sig_we_1 : std_logic;
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signal sig_oe_1 : std_logic;
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begin
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DUT: ram_dp port map(
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clk => sig_clk,
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address_0 => sig_address_0,
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data_0 => sig_data_0,
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cs_0 => sig_cs_0,
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we_0 => sig_we_0,
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oe_0 => sig_oe_0,
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address_1 => sig_address_1,
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data_1 => sig_data_1,
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cs_1 => sig_cs_1,
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we_1 => sig_we_1,
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oe_1 => sig_oe_1
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);
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mClkGen : clkGen port map(
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clk => sig_clk
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);
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stim: process
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begin
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sig_address_0 <= "00000000";
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sig_data_0 <= "00000000";
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sig_cs_0 <= '0';
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sig_we_0 <= '0';
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sig_oe_0 <= '0';
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sig_address_1 <="00000000";
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sig_data_1 <= "00000000";
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sig_cs_1 <= '0';
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sig_we_1 <= '0';
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sig_oe_1 <= '0';
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wait;
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end process stim;
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end tb; |