48 lines
1.2 KiB
VHDL
48 lines
1.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity single_port_ram is
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port
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(
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data : inout std_logic_vector(7 downto 0);
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addr : in std_logic_vector(15 downto 0);
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cs : in std_logic; -- chip select
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we : in std_logic; -- write enable
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oe : in std_logic; -- output enable
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clk : in std_logic
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);
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end entity;
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architecture rtl of single_port_ram is
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-- Build a 2-D array type for the RAM
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subtype word_t is std_logic_vector(7 downto 0);
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type memory_t is array(127 downto 0) of word_t;
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signal ram : memory_t;
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begin
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wr: process (clk) begin
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if (rising_edge(clk)) then
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if ( cs = '1' and we = '1') then -- write (= ram stores data from data input) when we = 1
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ram(to_integer(unsigned(addr))) <= data;
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end if;
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end if;
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end process;
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rd: process (clk) begin
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if (rising_edge(clk)) then
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if (cs = '1' and we = '0' and oe = '1') then -- read (= ram provides data at data ouput) only when we = 0 and oe = 1
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data <= ram(to_integer(unsigned(addr)));
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else
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data <= (others=>'Z'); -- IMPORTANT
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end if;
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end if;
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end process;
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end rtl;
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