79 lines
2.4 KiB
VHDL
79 lines
2.4 KiB
VHDL
-- Code your design here
|
|
library IEEE;
|
|
use IEEE.std_logic_1164.all;
|
|
|
|
entity FSM_sync is
|
|
port ( clk : in STD_LOGIC;
|
|
data_in : in STD_LOGIC;
|
|
direct : in STD_LOGIC;
|
|
invert : in STD_LOGIC;
|
|
data_out_sync : out STD_LOGIC);
|
|
end FSM_sync;
|
|
|
|
architecture beh of FSM_sync is
|
|
|
|
type state_t is (S_start,S_direct,S_invert);
|
|
|
|
signal state : state_t := S_start;
|
|
signal next_state : state_t := S_start;
|
|
|
|
signal dbg_state: std_logic_vector(1 downto 0); -- just for debugging (we can't see type state_t in the waveform viewer)
|
|
|
|
signal next_data_out : std_logic := '0';
|
|
|
|
begin
|
|
|
|
p_seq: process (clk)
|
|
begin
|
|
if (clk'event and clk ='1') then
|
|
state <= next_state;
|
|
data_out_sync <= next_data_out;
|
|
end if;
|
|
end process p_seq;
|
|
|
|
|
|
p_comb: process (state,data_in,direct,invert)
|
|
begin
|
|
case state is
|
|
when S_start => if direct AND NOT invert then
|
|
next_data_out <= data_in;
|
|
next_state <= S_direct;
|
|
elsif invert AND NOT direct then
|
|
next_data_out <= not data_in;
|
|
next_state <= S_invert;
|
|
else
|
|
next_data_out <= '0';
|
|
next_state <= S_start;
|
|
end if;
|
|
|
|
when S_direct => if direct and not invert then
|
|
next_state <= S_direct;
|
|
next_data_out <= data_in;
|
|
else
|
|
next_state <= S_start;
|
|
next_data_out <= '0';
|
|
end if;
|
|
|
|
when S_invert => if invert and not direct then
|
|
next_state <= S_invert;
|
|
next_data_out <= not data_in;
|
|
else
|
|
next_state <= S_start;
|
|
next_data_out <= '0';
|
|
end if;
|
|
end case;
|
|
|
|
end process p_comb;
|
|
|
|
-- just for debugging, we transform the state (type state_t) to a 2bit vector, which we can see in the waveform viewer
|
|
dbg: process (state)
|
|
begin
|
|
case state is
|
|
when S_start => dbg_state <= "00";
|
|
when S_direct => dbg_state <= "01";
|
|
when S_invert => dbg_state <= "10";
|
|
end case;
|
|
end process dbg;
|
|
|
|
|
|
end beh; |