14 lines
203 B
VHDL
14 lines
203 B
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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entity MyDesign is
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port (clk_i : in std_logic;
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data_i : in std_logic);
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end MyDesign;
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architecture behavior of MyDesign is
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begin
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end behavior; |