71 lines
1.8 KiB
VHDL
71 lines
1.8 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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-- the entity of the testbench is empty, no connection to the outer world
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entity testbench is
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end testbench;
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architecture tb of testbench is
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-- DUT (device under test = halfadder) component declaration
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component halfadder is
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port (a_i : in std_logic;
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b_i : in std_logic;
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sum_o : out std_logic;
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cy_o : out std_logic);
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end component;
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-- signals for the testbench
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signal sig_a, sig_b, sig_sum_out, sig_cy_out: std_logic;
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begin
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-- Connect DUT with tb signals
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DUT: halfadder port map(
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a_i => sig_a,
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b_i => sig_b,
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sum_o => sig_sum_out,
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cy_o => sig_cy_out);
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-- Process for DUT Test
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stimTest : process
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-- Procedure for applying an input vector
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procedure applyTv(inputs : in std_logic_vector (1 downto 0)) is
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begin
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sig_a <= inputs(0);
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sig_b <= inputs(1);
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wait for 10 ns;
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end procedure applyTv;
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-- Procedure for checking the outputs
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procedure check(outputs : in std_logic_vector (1 downto 0)) is
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begin
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assert (sig_sum_out = outputs(0))
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report "Testpattern " & std_logic'image(sig_a) & " " & std_logic'image(sig_b) & " Error in sum_out got " & std_logic'image(sig_sum_out) & " expected " & std_logic'image(outputs(0)) severity error;
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assert (sig_cy_out = outputs(1))
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report "Testpattern " & std_logic'image(sig_b) & " " & std_logic'image(sig_a) & " Error in cy_out got " & std_logic'image(sig_cy_out) & " expected " & std_logic'image(outputs(1)) severity error;
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end procedure check;
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begin
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-- Let's apply different input vectors and check the output
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applyTv("00");
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check("00");
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applyTv("01");
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check("01");
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applyTv("10");
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check("01");
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applyTv("11");
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check("10");
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wait;
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end process stimTest;
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end tb;
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