25 lines
895 B
VHDL
25 lines
895 B
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity minArith is
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port (a_i : in std_logic_vector (7 downto 0);
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b_i : in std_logic_vector (7 downto 0);
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ssum_o : out std_logic_vector (7 downto 0);
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sdiff_o : out std_logic_vector (7 downto 0);
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usum_o : out std_logic_vector (7 downto 0);
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udiff_o : out std_logic_vector (7 downto 0);
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ainc_o : out std_logic_vector (7 downto 0));
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end minArith;
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-- behavioral description of the halfadder given by two gates
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architecture behavior of minArith is
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begin
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ssum_o <= std_logic_vector(signed(a_i) + signed(b_i));
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sdiff_o <= std_logic_vector(signed(a_i) - signed(b_i));
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usum_o <= std_logic_vector(unsigned(a_i) + unsigned(b_i));
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udiff_o <= std_logic_vector(unsigned(a_i) - unsigned(b_i));
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ainc_o <= std_logic_vector(unsigned(a_i) + "00000001");
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end behavior; |