32 lines
1.1 KiB
VHDL
32 lines
1.1 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity LFSR is
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Port ( clk : in std_logic;
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value32 : out std_logic_vector (31 downto 0);
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value16 : out std_logic_vector (15 downto 0);
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value8 : out std_logic_vector ( 7 downto 0));
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end LFSR;
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architecture Behavioral of LFSR is
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signal rnd32 : std_logic_vector (31 downto 0) := (others=>'0');
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signal rnd16 : std_logic_vector (15 downto 0) := (others=>'0');
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signal rnd8 : std_logic_vector ( 7 downto 0) := (others=>'0');
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begin
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process begin
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wait until rising_edge(CLK);
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-- 8Bit
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rnd8(7 downto 1) <= rnd8(6 downto 0) ;
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rnd8(0) <= not(rnd8(7) XOR rnd8(6) XOR rnd8(4));
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-- 16Bit
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rnd16(15 downto 1) <= rnd16(14 downto 0) ;
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rnd16(0) <= not(rnd16(15) XOR rnd16(14) XOR rnd16(13) XOR rnd16(4));
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-- 32 Bit
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rnd32(31 downto 1) <= rnd32(30 downto 0) ;
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rnd32(0) <= not(rnd32(31) XOR rnd32(22) XOR rnd32(2) XOR rnd32(1));
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end process;
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value32 <= rnd32;
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value16 <= rnd16;
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value8 <= rnd8;
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end Behavioral; |