24 lines
361 B
VHDL
24 lines
361 B
VHDL
-- Clock Generator
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity clkGen is
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port (clk : out std_logic);
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end clkGen;
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architecture behavior of clkGen is
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constant clk_period : time := 10 ns;
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begin
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clkgen : process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process clkgen;
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end behavior; |