75 lines
1.8 KiB
VHDL
75 lines
1.8 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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--use IEEE.std_artih.all;
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entity testbench is
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end testbench;
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architecture tb of testbench is
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-- declare your DUT
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component gates is
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port( A,B,C,D : in std_logic;
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O : out std_logic);
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end component;
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-- needed signals
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signal sig_A, sig_B, sig_C, sig_D, sig_O: std_logic;
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begin
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-- Connect DUT with tb signals
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DUT: gates port map(
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A => sig_A,
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B => sig_B,
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C => sig_C,
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D => sig_D,
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O => sig_O);
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-- define process for testing our DUT
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gate_tester : process
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-- define a procedure (Slides 07) that applys input vector, waits and than checks output
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procedure check_sample(val_A, val_B, val_C, val_D, val_O : in std_logic) is
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begin
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-- apply signals to DUT inputs
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sig_A <= val_A;
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sig_B <= val_B;
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sig_C <= val_C;
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sig_D <= val_D;
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-- wait (at least 1 delta cycle)
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wait for 10 ns;
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-- check output of DUT and report possible error message
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assert (sig_O = val_O) report "Error for A= "
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& std_logic'image(val_A) & " B= "
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& std_logic'image(val_B) & " C= "
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& std_logic'image(val_C) & " D= "
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& std_logic'image(val_D) & ". Output is "
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& std_logic'image(sig_O) & " but should be "
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& std_logic'image(val_O) & "."
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severity failure;
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end procedure check_sample;
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begin
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-- now use procedure to check different combinations
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-- change this according to your solution
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-- (can also be done with loop, but we havn't learned that yet)
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check_sample('0','0','0','0','1');
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check_sample('0','0','0','1','0');
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check_sample('1','1','1','1','1');
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-- wait forever to stop process
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wait;
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end process gate_tester;
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end tb;
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