13 lines
474 B
VHDL
13 lines
474 B
VHDL
-- be aware of the correct order!
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-- EDA compiles from left to right
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-- 1) gate entities
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-- 2) architectures for the gate entities
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-- 3) Package (must be done after 1, because otherwise componante is not known)
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-- 4) your entity
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-- 5) your architecture (needs to know all above)
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-- 6) Testbench Entity
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-- 7) Testbench Architecture (in same file as testbench entity)
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-- This example is related to the first VELS taks using packages (if there is no package, skip step 1-3) |