34 lines
983 B
VHDL
34 lines
983 B
VHDL
-- Code your design here
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity fulladder_sel is
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port (afa_sel_i : in std_logic;
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bfa_sel_i : in std_logic;
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cinfa_sel_i : in std_logic;
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sumfa_sel_o : out std_logic;
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coutfa_sel_o : out std_logic);
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end fulladder_sel;
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architecture behavior of fulladder_sel is
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signal sig_INPUTS: STD_LOGIC_VECTOR(2 downto 0);
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signal sig_OUTPUTS: STD_LOGIC_VECTOR(1 downto 0);
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begin
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sig_INPUTS <= (cinfa_sel_i,bfa_sel_i,afa_sel_i);
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with sig_INPUTS select
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sig_OUTPUTS <= "00" when "000",
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"01" when "001",
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"01" when "010",
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"10" when "011",
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"01" when "100",
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"10" when "101",
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"10" when "110",
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"11" when "111",
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"XX" when others;
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sumfa_sel_o <= sig_OUTPUTS(0);
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coutfa_sel_o <= sig_OUTPUTS(1);
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end behavior; |