library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.Numeric_Std.all; architecture Behavioral of RAM is -- Die Länge der Adressen beträgt 6 Bit -> Länge/Größe des Vektors 64 -- die Länge der einzelnen Speicherzellen 8 Bit type memory_type is array (0 to 127) of std_logic_vector(17 downto 0); -- Der anfängliche Inhalt des Speichers ist Null. signal memory : memory_type := (others => (others => '0')); --constant for high Z constant high_z : std_logic_vector(35 downto 0) := "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; begin process (Clk) is variable addr1_int : INTEGER; variable addr2_int : INTEGER; begin if rising_edge(Clk) then output1 <= high_z; output2 <= high_z; addr1_int := to_integer(UNSIGNED(addr1)); addr2_int := to_integer(UNSIGNED(addr2)); if en_write = '0' then -- lesen if en_read1 = '1' then output1 <= memory(addr1_int+1) & memory(addr1_int); end if; if en_read2 = '1' then output2 <= memory(addr2_int+1) & memory(addr2_int); end if; --high Z wenn nur eins gelesen wird: if (en_read2 = '0') and (en_read1 = '1') then output2 <= high_z; elsif (en_read1 = '0') and (en_read2 = '1') then output1 <= high_z; end if; end if; -- schreiben if (en_write = '1') and (en_read1 = '0') and (en_read2 = '0') then memory(addr1_int) <= input; -- schreiben und lesen von addr2 elsif (en_write = '1') and (en_read1 = '0') and (en_read2 = '1') then --kann nur ausgeführ werden wenn addr1 != addr2 if not(addr1_int = addr2_int) and not(addr1_int = addr2_int+1) then memory(addr1_int) <= input; output2 <= memory(addr2_int+1) & memory(addr2_int); end if; end if; end if; end process; end Behavioral;