library IEEE;
use IEEE.std_logic_1164.all;
use work.fsm_pkg.all;

architecture behavior of fsm is

    signal current_state, next_state : work.fsm_pkg.fsm_state;
    signal next_output : std_logic_vector(1 downto 0);

begin
    
    process(CLK, RST)
    begin
        if rising_edge(CLK) then
            if RST = '1' then
                current_state <= START;
                OUTPUT <= "00";
            else
                current_state <= next_state;
                OUTPUT <= next_output;
            end if;
        end if;
    end process;
    
    process(current_state, INPUT)
    begin
        case current_state is
            when START =>
                if INPUT = "11" then
                    next_state <= S2;
                    next_output <= "00";
                    
                else
                    next_state <= START;
                    next_output <= "00";
                    
                end if;
                
            when S0 =>
                if INPUT = "00" then
                    next_state <= S2;
                    next_output <= "00";
                    
                elsif INPUT = "10" then
                    next_state <= S0;
                    next_output <= "11";
                    
                else
                    next_state <= S0;
                    next_output <= "00";
                    
                end if;
                
            when S1 =>
                if INPUT = "00" then
                    next_state <= S1;
                    next_output <= "00";
                    
                elsif INPUT = "10" then
                    next_state <= S2;
                    next_output <= "10";
                    
                else
                    next_state <= S1;
                    next_output <= "00";
                    
                end if;
                
            when S2 =>
                if INPUT = "00" then
                    next_state <= S0;
                    next_output <= "01";
                    
                elsif INPUT = "01" then
                    next_state <= S1;
                    next_output <= "10";
                    
                elsif INPUT = "10" then
                    next_state <= S2;
                    next_output <= "11";
                    
                else
                    next_state <= S2;
                    next_output <= "00";
                    
                end if;
                
        end case;
    end process;

    STATE <= current_state;

end behavior;