library IEEE;
use IEEE.std_logic_1164.all;
use work.IEEE_1164_Gates_pkg.all;

architecture behavior of gates is

    signal sig_g0, sig_g1, sig_g2, sig_g3  : std_logic;
    
begin
    
    
    G3: OR3 port map(
        I1 => A,
        I2 => not(B),
        I3 => C,
        O => sig_g3);
    
    G2: XOR3 port map(
        I1 => not(B),
        I2 => C,
        I3 => not(D),
        O => sig_g2);
    
    G1: OR3 port map(
        I1 => A,
        I2 => C,
        I3 => not(D),
        O => sig_g1);
    
    G0: AND3 port map(
        I1 => not(A),
        I2 => B,
        I3 => C,
        O => sig_g0);

    G4: OR4 port map(
        I1 => sig_g3,
        I2 => not(sig_g2),
        I3 => sig_g1,
        I4 => sig_g0,
        O => O);
    
end behavior;