-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;


entity testbench is
end testbench;

architecture tb of testbench is

component ram_dp is
port (
        clk       :in    std_logic;   
        address_0 :in    std_logic_vector (8-1 downto 0);  
        data_0    :inout std_logic_vector (8-1 downto 0); 
        cs_0      :in    std_logic;                       
        we_0      :in    std_logic;                     
        oe_0      :in    std_logic;                    
        address_1 :in    std_logic_vector (8-1 downto 0); 
        data_1    :inout std_logic_vector (8-1 downto 0);
        cs_1      :in    std_logic;                      
        we_1      :in    std_logic;                     
        oe_1      :in    std_logic                     
    );
end component;

component clkGen is
  port (clk : out std_logic);
end component;

signal sig_clk : std_logic;

signal sig_address_0 : std_logic_vector (8-1 downto 0);  
signal sig_data_0    : std_logic_vector (8-1 downto 0); 
signal sig_cs_0      : std_logic;                       
signal sig_we_0      : std_logic;                     
signal sig_oe_0      : std_logic;                    
        
signal sig_address_1 : std_logic_vector (8-1 downto 0); 
signal sig_data_1    : std_logic_vector (8-1 downto 0);
signal sig_cs_1      : std_logic;                      
signal sig_we_1      : std_logic;                     
signal sig_oe_1      : std_logic;


begin  
  DUT: ram_dp port map(
     clk => sig_clk,
     address_0 => sig_address_0,  
     data_0 => sig_data_0,
     cs_0 => sig_cs_0,                 
     we_0 => sig_we_0,                    
     oe_0 => sig_oe_0,                  
     address_1 => sig_address_1, 
     data_1 => sig_data_1, 
     cs_1 => sig_cs_1,            
     we_1 => sig_we_1,       
     oe_1 => sig_oe_1  
  );
  
  mClkGen : clkGen port map(
  	clk => sig_clk
  );

stim: process 
begin


     sig_address_0 <= "00000000";  
     sig_data_0 <= "00000000";
     sig_cs_0 <= '0';                 
     sig_we_0 <= '0';                    
     sig_oe_0 <= '0';                  
     sig_address_1 <="00000000";  
     sig_data_1 <= "00000000"; 
     sig_cs_1 <= '0';            
     sig_we_1 <= '0';       
     sig_oe_1 <= '0';  
 
   


wait;
end process stim;


end tb;