library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity single_port_ram is
	port
	(
		data	: inout std_logic_vector(7 downto 0);
        addr	: in std_logic_vector(15 downto 0);
        cs		: in std_logic; -- chip select
		we		: in std_logic; -- write enable
        oe		: in std_logic; -- output enable
		clk		: in std_logic
	);
	
end entity;

architecture rtl of single_port_ram is

	-- Build a 2-D array type for the RAM
	subtype word_t is std_logic_vector(7 downto 0);
	type memory_t is array(127 downto 0) of word_t;
	
	signal ram : memory_t;
	
begin


wr: process (clk) begin
        if (rising_edge(clk)) then
            if ( cs = '1' and we = '1') then             -- write (= ram stores data from data input) when we = 1
                ram(to_integer(unsigned(addr))) <= data;
            end if;
        end if;
    end process;
    
rd: process (clk) begin
        if (rising_edge(clk)) then
            if (cs = '1' and we = '0' and oe = '1') then  -- read (= ram provides data at data ouput) only when we = 0 and oe = 1
                data <= ram(to_integer(unsigned(addr)));
            else
                data <= (others=>'Z'); -- IMPORTANT
            end if;
        end if;
    end process;    
    
end rtl;