-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;


entity testbench is
end testbench;

architecture tb of testbench is

component single_port_ram is
port
	(
		data	: in std_logic_vector(7 downto 0);
        addr	: in std_logic_vector(15 downto 0);
		we		: in std_logic;
		clk		: in std_logic;
		q		: out std_logic_vector(7 downto 0)
	);
end component;

component clkGen is
  port (clk : out std_logic);
end component;

signal sig_clk : std_logic;
signal sig_addr : std_logic_vector(15 downto 0);
signal sig_q : std_logic_vector(7 downto 0);
signal sig_data : std_logic_vector(7 downto 0);
signal sig_we : std_logic;
use ieee.numeric_std.all;

begin  
  DUT: single_port_ram port map(
     clk => sig_clk,
     addr => sig_addr,
     data => sig_data,
     we => sig_we,
     q => sig_q
  );
  
  mClkGen : clkGen port map(
  	clk => sig_clk
  );

stim: process 

 procedure ReadRAM(read_addr : in integer) is
    begin
    sig_we <= '0';
    sig_addr <= std_logic_vector(to_unsigned(read_addr,16));
 end procedure ReadRAM;
 
 procedure WriteRAM(write_addr : in integer; write_data : in std_logic_vector(7 downto 0)) is
    begin
    sig_we <= '1';
    sig_addr <= std_logic_vector(to_unsigned(write_addr,16));
    sig_data <= write_data;
 end procedure WriteRAM;
   
   
begin

wait for 7 ns;

WriteRAM(2,"00000001");
wait for 20 ns;
WriteRAM(4,"00000010");
wait for 20 ns;
WriteRAM(6,"00000011");
wait for 20 ns;
WriteRAM(8,"00000100");
wait for 20 ns;
WriteRAM(10,"11111111");
wait for 30 ns;

ReadRAM(2);
wait for 20 ns;
ReadRAM(4);
wait for 20 ns;
ReadRAM(6);
wait for 20 ns;
ReadRAM(8);
wait for 20 ns;
ReadRAM(10);
wait for 20 ns;
ReadRAM(11);
wait for 20 ns;


wait;
end process stim;


end tb;