-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;


entity testbench is
end testbench;

architecture tb of testbench is

component single_port_rom is
port
    (
        addr    : in std_logic_vector(3 downto 0);
        q        : out std_logic_vector(4 downto 0)
    );
end component;


signal sig_addr : std_logic_vector(3 downto 0);
signal sig_q : std_logic_vector(4 downto 0);


begin  
  DUT: single_port_rom port map(
     addr => sig_addr,
     q => sig_q
  );
  


stim: process 
begin
sig_addr <= "0000";
wait for 10 ns;
sig_addr <= "0001";
wait for 10 ns;
sig_addr <= "0010";
wait for 10 ns;
sig_addr <= "0100";
wait for 10 ns;
sig_addr <= "1000";
wait;
end process stim;


end tb;